The present invention relates broadly to polishing articles such as pads for electrochemical mechanical polishing (ECMP), and more particularly to such articles which are formed of a layer of an electrically-conductive compound formulated as an admixture of a polymeric binder and an electrically-conductive filler.
In the general mass production of semiconductor devices, hundreds of identical “integrated” circuit (IC) trace patterns may be fabricated in several layers on a semiconducting wafer substrate which, in turn, is cut into hundreds of dies or chips. Within each of the die layers, the circuit traces, which are formed of a conductive material such as copper, aluminum, titanium, tantalum, iron, silver, gold, a conductively-doped semiconducting material, or the like, may be isolated from the next layer by an insulating material.
The fabrication of the IC trace patterns on the wafer thus may involve the deposition and removal of multiple layers of conducting, semiconducting, and/or dielectric materials. As the layers of these materials each is sequentially deposited and removed, the surface of the wafer may become relatively nonplanar. In order to assure the accuracy of the deposition and removal operations, and, ultimately, the performance of the semiconductor device, it is necessary to polish the layers to a smooth surface topography or, as is termed in the vernacular, a high degree of planarity, the terms “polish” and “planarize” often being used interchangeably, and are so used herein. In this regard, a relatively rough surface topography may be manifested as a depth of field problem resulting in poor resolution of the patterns of subsequently deposited layers, and, in the extreme, in the short circuiting of the device. As circuit densities in semiconductor dies continue to increase, any such defects become unacceptable and may render the circuit either inoperable or lower its performance to less than optimal.
To achieve the relatively high degree of planarity required for the production of substantially defect free IC dies, a chemical-mechanical polishing (CMP) process has been routinely practiced. Such process involves chemically etching the wafer surface in combination with mechanical polishing or grinding. This combined chemical and mechanical action allows for the controlled removal of material and the polishing, i.e., planarizing, of the wafer.
In essential operation, CMP is accomplished by holding the semiconductor wafer against a rotating polishing surface, or otherwise moving the wafer relative to the polishing surface, under controlled conditions of temperature, pressure, and chemical composition. The polishing surface, which may be a planar pad formed of a relatively soft and porous material such as a blown polyurethane, is wetted with a chemically reactive and abrasive aqueous slurry. The aqueous slurry, which may be either acidic or basic, typically includes abrasive particles, a reactive chemical agent such as a transition metal chelated salt or an oxidizer, and adjuvants such as solvents, buffers, and passivating agents. Within the slurry, the salt or other agent provides the chemical etching action, with the abrasive particles, in cooperation with the polishing pad, providing the mechanical polishing action.
An abrasive also may be incorporated into the pad itself, such pads being termed “fixed abrasive” pads. When used in conjunction with these fixed abrasive pads, the slurry may provide additional abrasive or, alternatively, with the abrasive being supplied only by the pad, the slurry may be provided instead as a substantially abrasive-free solution. For the purposes of the present description, however, the terms “slurry” and “solution” may be used interchangeably unless otherwise indicated.
The basic CMP process is further described in the articles Derbyshire, K., “Making CMP Work,” Semiconductor Magazine, pp. 40–53, July 2002; “The Semiconductor Equipment Business,” Prismark Partners LLC, Cold Spring Harbor, N.Y., March 2002; and “CMP,” Prismark Partners, LLC, Cold Spring Harbor, N.Y., November 2000, and in the following U.S. Pat. Nos. 5,709,593; 5,707,274; 5,705,435; 5,700,383; 5,665,201; 5,658,185; 5,655,954; 5,650,039; 5,645,682; 5,643,406; 5,643,053; 5,637,185; 5,618,227; 5,607,718; 5,607,341; 5,597,443; 5,407,526; 5,395,801; 5,314,843; 5,232,875; and 5,084,071. Polishing pads are further described in the following references: U.S. Pat. Nos. 3,760,637; 4,198,739; 4,462,188; 4,588,421; 4,728,552; 4,752,628; 4,841,680; 4,927,432; 4,959,113; 4,964,919; 5,230,833; 5,257,478; 5,264,010; 5,329,734; 5,382,272; 5,389,352; 5,476,606; 5,480,476; 5,487,697; 5,489,233; 5,534,053; 5,578,362; 5,605,760; 5,624,303; 5,645,474; 5,664,989; 5,693,239; 5,707,492; 5,738,567; 5,738,800; 5,769,689; 5,770,103; 5,795,218; 5,823,855; 5,860,848; 5,876,266; 5,879,222; 5,882,251; 5,900,164; 5,913,713; 5,932,486; 5,938,801; 5,976,000; 5,989,470; 6,001,269; 6,017,265; 6,019,666; 6,022,264; 6,022,268; 6,030,899; 6,036,579; 6,042,741; 6,054,017; 6,062,968; 6,609,080; 6,071,178; 6,074,546; 6,093,649; 6,095,902; 6,099,394; 6,099,954; 6,106,754; 6,117,000; 6,120,366; 6,126,532; 6,132,647; 6,143,662; 6,174,227; 6,159,088; 6,165,904; 6,168,508; 6,171,181; 6,179,950; 6,210,254; 6,210,525; 6,217,418; 6,217,434; 6,218,305; 6,231,434; 6,238,271; 6,241,586; 6,245,679; 6,261,168; 6,267,659; 6,277,015; 6,284,114; 6,287,174; 6,287,185; 6,293,852; 6,294,473; 6,315,645; 6,315,857; 6,319,370; 6,325,703; 6,332,832; 6,346,032; 6,354,915; 6,358,130; 6,358,854; 6,364,749; and 6,375,559; U.S. Patent Application Publication Nos. 2001/0000497; 2001/0024878; 2001/0031610; 2001/0031615; and 2002/0028646; European Patent Nos. 0,919,330 and 1,112,816; International Application Nos. WO 98/47662; WO 00/02707; WO 00/71297; WO 01/19567; WO 01/24969; WO 01/49449 and WO 02/13248; and Patent Abstracts of Japan Nos. 0728944; 11055246; 10055684; 2000134529; 09305885; 09305884; 11040226; 2000153142; 11111126; 10084230; 09246709; 09265998; 10242900; 10294459; 11159839; 1159841; 11241636; and 11281153.
Looking to FIG. 1, a representative CMP process and apparatus are illustrated schematically at 10. The apparatus 10, which is illustrated to be of a “rotational”-type, includes a wafer carrier, 12, for holding a semiconductor wafer or other workpiece, 14. A polishing pad, 16, is positioned between wafer carrier 12 and wafer 14, with the wafer being held against the pad by a partial vacuum, frictionally, or with an adhesive. Wafer carrier 12 is provided to be continuously rotated by a drive motor, 18, in the direction referenced at 20, and additionally may be reciprocated transversely in the directions referenced at 22. In this regard, the combined rotational and transverse movements of the wafer 14 are intended to reduce the variability in the material removal rate across the work surface 23 of the wafer 14.
Apparatus 10 additionally includes a platen, 24, which is rotated in the direction referenced at 26, and on which is mounted a polishing pad, 28. As compared to wafer 14, platen 24 is provided as having a relatively large surface area to accommodate the translational movement of the wafer on the carrier 12 across the surface of the polishing pad 28.
A supply tube, 30, is mounted above platen 26 to deliver a stream of polishing slurry, referenced at 32, which is dripped or otherwise metered onto the surface of pad 28 from a nozzle or other outlet, 34, of the tube 30. The slurry 32 may be gravity fed from a tank or reservoir (not shown), or otherwise pumped through supply tube 30. Alternatively, in an “orbital” variant of apparatus 10 (not shown), slurry 32 may be supplied from below platen 26 such that it flows upwardly from the underside of polishing pad 28 and through holes which may be formed in the pad 28. Apparatus 10 also may be provided to be of a continuous belt-type.
Increasingly, the planarization of the surfaces of the metal layers deposited on the wafer is assisted by the use of an electrolytic polishing slurry or solution by means of a process known as electrochemical mechanical planarization (ECMP). With continuing reference to FIG. 1, a deposited metal layer of the wafer 14, which layer may be considered for present purposes to be the work surface 23, the electrolytic slurry or solution 32, and a cathode electrode, 40, which is coupled to or otherwise is in contact with the pad 28, are connected to a voltage potential source, 42, to complete an electrochemical circuit or cell, referenced at 44. With a bias applied between the cathode 40 and the surface 23, material in the form of metal ions may be removed by the disassociative oxidation from the surface 23 which functions as an anode in the circuit 44. These ions, which dissolve or otherwise into the slurry 32, then may either plate at the cathode 40 or be washed away with the slurry. The rate at which the material is removed generally is determined by the control of such system parameters as the concentration of electrolyte in the slurry 32 and the voltage potential applied by the source 42. The ECMP process is further described in the following references: U.S. Pat. Nos. 6,482,307; 6,379,223, 6,368,190, 6,299,741, 5,911,619, and 5,807,165; U.S. 2002/0102853; WO 02/085570, 02/075804, 02/084714, 01/71796, and 01/63018; and EP 1,103,346.
It has been observed, however, that when utilized in ECMP tools or systems, conventional polishing pads, which typically are formed of non-electrically conductive materials, may interfere with the application of the bias to the work surface. The result is a non-uniform or variable dissolution of material from the work surface. Accordingly, it is believed that improved conductive polishing pads would be well-received by the semiconductor manufacturing industry. Especially desired would be a pad offering improved performance life when used in ECMP tools or systems.